View STK6011_435500.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

STK6011
DATA SHEET by SYNTEK(R)
DESIGN CENTER
6F, YU FENG BLDG. 317 SUNG-CHANG RD., TAIPEI, TAIWAN, R.O.C. TEL: 886-2-25056383 FAX: 886-2-25064323 HEADQUARTER TEL: 886-3-5773181 FAX: 886-3-5778010
U t4 e =========STK6011========= e 8051 Embedded Microcontroller h S ta a .D w w w
Version 1.0
.c
m o
3F, NO.24-2, INDUSTRY E.RD., IV, SCIENCE-BASED INDUSTRIAL PARK, HSINCHU, TAIWAN, R.O.C.
(c) Copyrriightt SYNTEKT SEMIICONDUCTOR Corrporrattiion & Liicensorrs ((2000))..Alll rriightts rreserrved (c) Copy gh SYNTEKT SEM CONDUCTOR Co po a on & L censo s 2000 A gh s ese ved 1
w
w
w
.D
a
aS t
ee h
4U t
om .c
STK6011
Caution!
The information in this document is subject to change without notice and does not represent a commitment on part of the vendor, who assumes no liability or responsibility for any errors that may appear in this data sheet. No warranty or representation, either expressed or implied, is made with respect to the quality, accuracy, or fitness for any particular part of this document. In no event DCNT the manufacturer be liable for direct, indirect, special, incidental or consequential damages arising from any defect or error in this data sheet or product. Product names appearing in this data sheet are for identification purpose only, and trademarks and product names or brand names appearing in this document are property of their respective owners. This data sheet contains materials protected under International Copyright Laws. All rights reserved. No part of this data sheet may be reproduced, transmitted, or transcribed without the expressed written permission of the manufacturer and authors of this data sheet.
2
STK6011
STK6011 Data Sheet Table of Contents Item Page 1. GENERAL DESCRIPTION.................................................................................. 5 2. FEATURES .......................................................................................................... 5 3. BLOCK DIAGRAM ............................................................................................. 5 4. PIN CONNECTION ............................................................................................. 6 5. PIN CONFIGURATION....................................................................................... 8 6. POWER CONFIGURATION ............................................................................... 8 7. PINS DESCRIPTION ........................................................................................... 9 8. FUNCTIONAL DESCRIPTIONS ......................................................................... 10 8.1 8051 CPU Core.......................................................................................................10 8.2 Allocation of Memory ............................................................................................10 8.2.1 Internal Special Function Registers (SFR).......................................................... 10 8.2.2 Internal RAM ............................................................................................................ 11 8.2.3 Auxiliary RAM (AUXRAM) .................................................................................. 11 8.2.4 External Special Function Registers (XFR)........................................................ 11 8.3 Pad Function Control ............................................................................................12 8.4 I/O Port ..................................................................................................................12 8.4.1 Port0, 1, 2, 3................................................................................................................ 12 8.4.2 Port4............................................................................................................................. 13 8.5 PWM DAC .............................................................................................................13 8.6 A/D Converter........................................................................................................13 8.7 Low Power Reset (LVR).........................................................................................14 8.8 Watchdog Timer ....................................................................................................14 8.9 Power Management ...............................................................................................14 8.9.1 Idle Mode ...................................................................................................................... 14 8.9.2 Power-down Mode ...................................................................................................... 15 8.9.3 Reduce EMI Emission (Disable ALE output)....................................................... 15 8.10 In-System Programming Function (ISP) ............................................................15 8.10.1 ISP Control Block ..................................................................................................... 15 8.10.2 Start to ISP Data Write/Read................................................................................. 16 8.10.3 Cyclic Redundancy Check (CRC)......................................................................... 17 9. MEMORY MAP of XFR ....................................................................................... 18 10. ELECTRICAL PARAMETERS.......................................................................... 19 10.1 DC Characteristics...............................................................................................19
3
STK6011
10.2 AC Characteristics...............................................................................................19 10.3 Absolute Maximum Ratings ................................................................................19 10.4 Operating Conditions Allowable .........................................................................19
11. PACKAGE DIMENSION ................................................................................... 20 11.1 40-Pin PDIP 600 Mil.............................................................................................20 11.2 42-Pin SDIP Unit ..................................................................................................20 11.3 44-Pin PLCC Unit ................................................................................................21 11.4 44-Pin QFP Unit ...................................................................................................22 11.5 48-Pin LQFP Unit.................................................................................................23 12. ORDER INFORMATION................................................................................... 24 13. CONTACT INFORMATION .............................................................................. 24
4
STK6011
1. GENERAL DESCRIPTION The STK6011 is an 8-bit micro-controller, which is compatible with the industry standard 8051 CPU. It consists of an 8051 CPU core, a 64k-byte internal program Flash ROM support to ISP function, a 1024-byte SRAM, four 8-bit I/O ports, an extra 4-bit I/O port, two 16-bit timer/counter, an UART serial port, five interrupt source, a watchdog timer, 5 built PWM DACs, and a 4-channel A/D converter.
2. FEATURES
* * * * * * * * * * * *
Industry 8051 core 36 bi-directional I/O pins (max.) 5 channels of PWM DAC (max.) 4 channels of 6-bit ADC (max.) 64K bytes of program Flash ROM support to In-System Programming (ISP) 1024 bytes of SRAM Watchdog timer featuring programmable interval Built-in lower power reset circuit Power-down wakeup by interrupt (INT0# or INT1#) Flash ROM program code protection 5V/3.3V power supply with bonding option Package designed with 40-pin DIP, 42-pin SDIP, 44-pin PLCC, 44-pin QFP, or 48-pin LQFP
3. BLOCK DIAGRAM
P0.0~7
P0.0~7 P2.0~7 RD WR ALE
P0.0~P0.7 P1.0~P1.7 P2.0~P2.7 P3.0~P3.7 P4.0~P4.7
AUXRAM
XADR XRD XWR
P2.0~7 RD WR ALE
AD0~3
XFR CONTROL ADC
EA# PSEN# ALE
8051 CORE WATCHDOG TIMER
RST X1 X2
DA0~4
PWM DAC
5
STK6011
4. PIN CONNECTION
P1.0/PWM0 P1.1/PWM1 P1.2/PWM2 P1.3/PWM3 P1.4/PWM4 P1.5 P1.6 P1.7 RST P3.0/RXD P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 P3.6/WR# P3.7/RD# X2 X1 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 Pin PDIP
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 EA# ALE PSEN# P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
P4.2/AD2 P1.0/PWM0 P1.1/PWM1 P1.2/PWM2 P1.3/PWM3 P1.4/PWM4 P1.5 P1.6 P1.7 RST P3.0/RXD P3.1/TXD 0 P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 P3.6/WR# P3.7/RD# X2 X1 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 Pin SDIP
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VDD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 EA# ALE PSEN# P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P4.0/AD0
P1.4/PWM4 6 P1.5 P1.6 P1.7 RST P3.0/RXD P4.3/AD3 P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 7 8 9 10 11 12 13 14 15 16 17 18 P3.6/WR#
P1.3/PWM3 5 19 P3.7/RD#
P1.2/PWM2 4 20 X2
P1.1/PWM1 3 21 X1
P1.0/PWM0 2 22 VSS
44 Pin PLCC
6
P4.2/AD2 1 23 P4.0/AD0
P0.1 P0.0 43 25 42 26 P2.2 P2.1
P0.2
P0.3
VDD 44 24 P2.0
41 27 P2.3
40 39 38 37 36 35 34 33 32 31 30 29 28 P2.4 P0.4 P0.5 P0.6 P0.7 EA# P4.1/AD1 ALE PSEN# P2.7 P2.6 P2.5
STK6011
P1.4/PWM4 44 P1.5 P1.6 P1.7 RST P3.0/RXD P4.3/AD3 P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 1 2 3 4 5 6 7 8 9 10 11 12 P3.6/WR# NC 48 P1.5 P1.6 P1.7 RST P3.0/RXD P4.3/AD3 P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 P3.6/WR#
P1.3/PWM3 43 13 P3.7/RD#
P1.2/PWM2 42 14 X2
P1.1/PWM1 41 15 X1
P4.2/AD2 P1.0/PWM0 40 16 VSS 39 17 P4.0/AD0
P0.0 37 19 P2.1
P0.1 36 20 P2.2
P0.2
P0.3
44 Pin QFP
VDD 38 18 P2.0
35 21 P2.3
34 33 32 31 30 29 28 27 26 25 24 23 22 P2.4 P0.4 P0.5 P0.6 P0.7 EA# P4.1/AD1 ALE PSEN# P2.7 P2.6 P2.5
P1.4/PWM4 47 14 P3.7/RD#
P1.3/PWM3 46 15 X2
P1.2/PWM2 45 16 X1
P1.1/PWM1 44 17 VSS
48 Pin LQFP
P1.0/PWM0 43 18 P4.0/AD0
P4.2/AD2 42 19 P2.0
P0.1 P0.0 40 21 39 22 P2.3
P0.2
P0.3
VDD 41 20
38 23 P2.4
37 36 35 34 33 32 31 30 29 28 27 26 25 24 NC P0.4 P0.5 P0.6 P0.7 EA# P4.1/AD1 ALE PSEN# P2.7 P2.6 P2.5
P2.2 P2.1
NC
7
STK6011
5. PIN CONFIGURATION "Open drain pin" means the pin may sink at least 4mA current but drive only 10~20uA to VDD. It may be used as input or output function and needs an external pull-up resistor. "CMOS output" means the pin may sink at least 4mA and drive. It is not preferred to use such a pin as input function. "8051 standard pin" is a pseudo-open drain pin. It may sink at least 4mA current when output stays at a low level, and drives at least 4mA current for 2 X'tal period when output changes from a low level to a high level, and then drives at 120A for a high level. It can be used as input or output function and needs an external pull-up resistor when driving a device with heavy load.
4mA 2 OSC period delay
120u
4mA Pin Output D 4mA Output D
No
Pin Input Data 4mA
Pin
4mA Output D
Input Data
8051 Standard Pin
CMOS Output Pin
Open Drain Pin
6. POWER CONFIGURATION The STK6011 works in a system with a 5V or 3.3V power supply by bonding option. In a 5V-power option, the VDD pin is connected to a 5V power supply, all output pins changes from 0 to 5V, and input pins can accept a voltage ranging from 0 to 5V. The voltage range of ADC conversion is 5V. However, the X1 and X2 pins operate below 3.3V. In a 3.3V power option, VDD pin is connected to 3.3V power, all output pins change from 0 to 3.3V, and all input pins only allow input ranging from 0 to 3.3V. The voltage range of ADC conversion is 3.3V.
8
STK6011
7. PINS DESCRIPTION Name P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0/PWM0 P1.1/PWM1 P1.2/PWM2 P1.3/PWM3 P1.4/PWM4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0/RXD P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 P3.6/WR# P3.7/RD# P4.0/AD0 P4.1/AD1 P4.2/AD2 P4.3/AD3 VDD VSS X2 X1 RST ALE PSEN# EA# I/O Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I I O O I Description General purpose I/O (open drain) General purpose I/O (open drain) General purpose I/O (open drain) General purpose I/O (open drain) General purpose I/O (open drain) General purpose I/O (open drain) General purpose I/O (open drain) General purpose I/O (open drain) General purpose I/O (8051 standard) / PWM DAC output (CMOS) General purpose I/O (8051 standard) / PWM DAC output (CMOS) General purpose I/O (8051 standard) / PWM DAC output (CMOS) General purpose I/O (8051 standard) / PWM DAC output (CMOS) General purpose I/O (8051 standard) / PWM DAC output (CMOS) General purpose I/O (8051 standard) General purpose I/O (8051 standard) General purpose I/O (8051 standard) General purpose I/O (8051 standard) General purpose I/O (8051 standard) General purpose I/O (8051 standard) General purpose I/O (8051 standard) General purpose I/O (8051 standard) General purpose I/O (8051 standard) General purpose I/O (8051 standard) General purpose I/O (8051 standard) General purpose I/O / RXD (8051 standard) General purpose I/O / TXD (8051 standard) General purpose I/O / INT0# (8051 standard) General purpose I/O / INT0# (8051 standard) General purpose I/O / T0 (8051 standard) General purpose I/O / T1 (8051 standard) General purpose I/O / WR# (8051 standard) General purpose I/O / RD# (8051 standard) General purpose I/O (8051 standard) / ADC Input General purpose I/O (8051 standard) / ADC Input General purpose I/O (8051 standard) / ADC Input General purpose I/O (8051 standard) / ADC Input Power Supply Ground Oscillator output Oscillator input Active-high reset Address Latch Enable Program Store Enable External Access Enable
Ps: See "5. PIN CONFIGURATION" for detail description of different pin output type.
9
STK6011
8. FUNCTIONAL DESCRIPTIONS 8.1 8051 CPU Core The CPU core of STK6011 is compatible to industry 8051 standard, and it consists of 256 bytes of RAM, special function registers (SFR), two timers, five interrupt sources, and a serial interface. The CPU core catches its program code from a 64K-byte Flash in STK6011. When CPUclk is set, the CPU core can work at a double rate. And then the CPU operates as if a double-frequency crystal is applied to STK6011.
Note: Listed in this data sheet, all registers are collected in the external RAM area of 8051. You may refer to the 8051 specifications for an internal RAM memory map in detail. 8.2 Allocation of Memory 8.2.1 Internal Special Function Registers (SFR) The SFR are the same as that of 8051 standard, except the P4 (D8h) and CHIPCON (BFh) registers.
STK6011 Special Function Registers F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 B ACC P4 PSW FF F7 EF E7 DF D7 CF C7 CHIPCON BF B7 AF A7 9F 97 8F PCON 87 Bit 2 P42 CPUclk Bit 1 P41 Bit 0 P40
IP P3 IE P2 SCON P1 TCON P0
SBUF TMOD SP Bit 7 TL0 DPL Bit 6 TL1 DPH Bit 5 TH0 TH1
Reg. Name P4 CHIPCON
Addr. D8h(r/w) BFh(w)
Bit 3 P43 XRAMen ALEdis
Bit 4
P4 (r/w) : Port4 is a bit addressable I/O port. Its usage is similar to other ports', all standing for "1" in Chip 10
STK6011
Reset.
CHIPCON (w): Chip Configuration Register, all standing for "0" in Chip Reset XRAMen = 1 To enable the on-chip AUXRAM = 0 To disable the on-chip AUXRAM ALEdis = 1 To disable pin ALE output for low EMI = 0 To enable pin ALE output CPUclk = 1 CPU working at a double rate = 0 CPU working at a normal rate 8.2.2 Internal RAM (256 Bytes) 256 bytes of the internal RAM kept in STK6011 are the same as that of 8052 standard.
8.2.3 Auxiliary RAM (AUXRAM, 768 Bytes) Total 768 bytes of the auxiliary RAM is configured in the 8051 external data memory area 0000h - 02FFh. Programs can use the "MOVX @Ri" instruction to access the AUXRAM memory area 0000h - 00FFh, or "MOVX @DPTR" instruction to access the AUXRAM full memory area 0000h - 02FFh. The AUXRAM is disabled after a reset. Setting the "XRAMen" bit in CHIPCON register will enable the access to AUXRAM. When AUXRAM is enabled, the "MOVX" instruction will always access to on-chip AUXRAM. At the time of execution from internal program memory, an access to AUXRAM will not affect the Port0, Port2, WR# and RD#.
8.2.4 External Special Function Registers (XFR) The XFR is a group of registers configured in the 8051 external RAM area 0F00h - 0FFFh for the special functions. Programs can use the "MOVX " instruction to access these registers.
FFh
Internal RAM
Accessible by indirect addressing only (Using MOV A,@Ri instruction)
SFR
Accessible by direct addressing
XFR
Accessible by indirect external RAM addressing (Using MOVX instruction)
0FFF h
80h 7Fh
0F00h 02FFh
Internal RAM
Accessible by direct and indirect addressing
AUXRAM
Accessible by indirect external RAM addressing (Using MOVX instruction
00h
0000h
11
STK6011
8.3 Pad Function Control The Chip Configuration registers explain the chip configuration and the pin function. Reg. Name Addr. PADOPT 0F50h(w) PADOPT 0F51h(w) Bit 7 PWMf Bit 6 PWMd Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 AD3E AD2E AD1E AD0E PWM4E PWM3E PWM2E PWM1E PWM0E Bit 4
PADOPT (w): control registers in a pad mode, all standing for "0" in Chip Reset AD3E = 1 Pin "P4.3/AD3" for AD3 = 0 Pin "P4.3/AD3" for P4.3 AD2E = 1 Pin "P4.2/AD2" for AD2 = 0 Pin "P4.2/AD2" for P4.2 AD1E = 1 Pin "P4.1/AD1" for AD1 = 0 Pin "P4.1/AD1" for P4.1 AD0E = 1 Pin "P4.0/AD0" for AD0 = 0 Pin "P4.0/AD0" for P4.0 PWMf = 1 Selection of 94KHz PWM frequency = 0 Selection of 47KHz PWM frequency PWMd = 1 PWM pulse width for 253-step resolution = 0 PWM pulse width for 256-step resolution PWM4E = 1 Pin "P1.4/PWM4" for PWM4 = 0 Pin "P1.4/PWM4" for P1.4 PWM3E = 1 Pin "P1.3/PWM3" for PWM3 = 0 Pin "P1.3/PWM3" for P1.3 PWM2E = 1 Pin "P1.2/PWM2" for PWM2 = 0 Pin "P1.2/PWM2" for P1.2 PWM1E = 1 Pin "P1.1/PWM1" for PWM1 = 0 Pin "P1.1/PWM1" for P1.1 PWM0E = 1 Pin "P1.0/PWM0" for PWM0 = 0 Pin "P1.0/PWM0" for P1.0 8.4 I/O Port 8.4.1 Port 0, 1, 2, 3 Port0 is a group of open drain pins, which is the same as that of 8051 standard. Port1 is a group of pseudo-open drain pins, which is the same as that of 8051 standard if general12
STK6011
purpose I/O port function is selected, or as CMOS output pins if PWM function is selected. Port2, 3 are groups of pseudo-open drain pins, which is the same as that of 8051 standard.
8.4.2 Port 4 Port4 is a bit addressable I/O port. Its usage is similar to other ports'.
8.5 PWM DAC Each 8-bit PWMDA register in XFR controls each output pulse width of PWM DAC converter. PWMf selects the frequency of PWM clock as 47KHz or 94KHz (for X'tal frequency = 12MHz), and PWMd selects the total duty cycle step of these DAC outputs as 253 or 256. In case of PWMd=1, writing FDH/FEH/FFH to DAC register makes output stably high. Writing 00H to DAC register makes the output stably low. Reg. Name PWMDA PWMDA PWMDA PWMDA PWMDA Addr. 0F20h(r/w) 0F21h(r/w) 0F22h(r/w) 0F23h(r/w) 0F24h(r/w) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Pulse width of PWM DAC 0 Pulse width of PWM DAC 1 Pulse width of PWM DAC 2 Pulse width of PWM DAC 3 Pulse width of PWM DAC 4 Bit 1 Bit 0
PWMDA (r/w): The mentioned-above output pulse width control is used for DA0-4. All of PWM DAC converters, after powered on, center on value 80h.
8.6 A/D converter The STK6011 is installed with four 6-bit A/D converters in VDD ranges. Software can choose a current converting channel by setting the SAD3/SAD2/SAD1/SAD0 bits. The refresh rate of the ADC may be gained by OSC freq./1536 (128s for 12MHz crystal). The voltage on the input pin is compared with the voltage on the internal VDD x N / 64, where N=0-63, by the ADC. The ADC output value is N when pin voltage is higher than VDD x N / 64 and lower than VDD x (N+1) / 64. Reg. Name Addr. ADC 0F10h (R) ADC 0F10h (w) ADC (w): ADC control. ENADC = 1 To enable the ADC SADC0 = 1 To select the ADC0 pin input SADC1 = 1 To select the ADC1 pin input SADC2 = 1 To select the ADC2 pin input 13 Bit 7 EADC Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ADC converting result SAD3 SAD2 SAD1 Bit 0 SAD0
STK6011
SADC3 = 1 To select the ADC3 pin input ADC (r): ADC converting result 8.7 Low Power Reset (LVR) The Low Power Reset has a chip reset signal increase when the voltage level of power supply goes below 75% of VDD in a specific period of time. After the voltage level of power supply rises above 75% of VDD, LVR stays at a reset state for 414 crystal cycles and make sure the chip exits from reset condition with a stable crystal oscillation.
8.8 Watchdog Timer When Watchdog Timer overflows, it automatically ensures a device reset. The overflow interval is gained by 0.25 sec x N, in which N is a number ranging from 1 to 8, and it can be programmed by way of register WDT2-0. Since the timer function is disabled after power-on reset, users may enable this function by setting EWDT and clear the timer by setting WDTclr. Reg. Name Addr. WDT 0F18h (w) Bit 7 EWDT Bit 6 WDTclr Bit 5 Bit 4 Bit 3 Bit 2 WDT2 Bit 1 WDT1 Bit 0 WDT0
WDT (w): Watchdog Timer control register. EWDT = 1 To enable the Watchdog Timer WDTclr = 1 To clear the Watchdog Timer WDT2: WDT0 = 0 Overflow interval = 8 x 0.25 sec. = 1 Overflow interval = 1 x 0.25 sec. = 2 Overflow interval = 2 x 0.25 sec. = 3 Overflow interval = 3 x 0.25 sec. = 4 Overflow interval = 4 x 0.25 sec. = 5 Overflow interval = 5 x 0.25 sec. = 6 Overflow interval = 6 x 0.25 sec. = 7 Overflow interval = 7 x 0.25 sec. (The list above is based on X'tal frequency = 12MHz)
8.9 Power Management 8.9.1 Idle Mode Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to the 8051 CPU core is stopped. The peripherals and the interrupt logic continue to be clocked. The CPU core will exit from the idle mode when either an interrupt or a reset occurs. 14
STK6011
8.9.2 Power-down Mode When the PD bit in the PCON register is set, the 8051 CPU core enters the power-down mode. In this mode, all of the clocks, including the X'tal oscillator, are stopped. To exit from the power-down mode, use a hardware reset or external interrupts INT0# to INT1# when enabled and set to level triggered. If the external interrupt signal is longer than the X'tal oscillator stable time, the program will execute the interrupt service routine. If the external interrupts signal is shorter than the X'tal oscillator stable time, the program will execute the next PC.
8.9.3 Reduce EMI Emission (Disable ALE output) The STK6011 allows users to reduce the EMI emission by setting the ALEdis bit in the CHIPCON register. This function will disable the clock signal in Fosc/6 Hz output to the ALE pin.
8.10 In-System Programming Function (ISP) The STK6011 uses 8051 UART ports (P3.0/RXD, P3.1/TXD) to execute ISP function. The P3.0/RXD pin works as SCL pin of I2C slave device, and the P3.1/TXD pin works as SDA pin of I2C slave device. The features of ISP are outlined below: 1. Block Erase: 128 Byte, 10ms 2. Whole Flash erase: 100ms 3. Byte programming Cycle time: 40s per byte 4. Whole 64K-byte Flash programming within 6 sec. 5. CRC check. After Power On/Reset, The STK6011 runs the original Program Code. Once the S/W detects an ISP request, S/W can accept the request following the steps below: 1. Clear watchdog and disable all interrupts. 2. Write ISP control block slave address to ISPSLV. 3. Write 93h to the ISP enable register (ISPEN) to enable ISP. 4. Enter 8051 idle mode immediately. When ISP is enabled, the STK6011 enters into ISP mode for 15-22.5s. In the mode, PWM DACs and I/O pins keep running at their former status. Reg. Name Addr. ISPSLV 0F0Bh(w) ISPEN 0F0Ch(w) 8.10.1 ISP Control Block STK6011 built in an ISP control block that is an I2C slave device. By this block, users can treat the 64K15 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 ISP Control Block Slave Address Write 93h to enable the ISP mode Bit 1 Bit 0
STK6011
byte Flash as 32 EEPROM (like 24C16, called "EEPROM_like" in this data sheet). There are two types of I2C bus transfer in this block: Write: S-ttttttt0k-000000wwk-ddddddddk-P Read: Where S = start ttttttt = ISP Control Block Slave Address k = ack by slave dddddddd = data CCCCCCCC = crc_register[15:8] Addr. 00h(w) 01h(w) 02h(w) 00h(w): SDP = 1 To enable the S/W data protection of Flash. User needs to set this bit at the end of ISP mode SDUP = 1 To disable the S/W data protection of Flash. User needs to set this bit at the start of ISP mode ERASE = 1 To erase one page (128-byte) of Flash BLANK = 1 To erase whole Flash CRCclr = 1 To clear CRC register CPUclr = 1 To reset STK6011 Above 6 bits will be cleared by I2C STOP condition. And only one bit can be set to 1 at the same time. 01h(w): BANK4 - 0: EEPROM_like bank selection. Choice any one of EEPROM_like to access. 02h(w): EPSladr : EEPROM_like slave address Bit 7 SDP Bit 6 SDUP Bit 5 ERASE Bit 4 BLANK BANK4 cccccccc = crc_register[7:0] Bit 3 BANK3 Bit 2 BANK2 Bit 1 CRCclr BANK1 Bit 0 CPUclr BANK0 P = stop ww = word address K = ack by host ( 0 or 1) S-ttttttt1k-CCCCCCCCK-ccccccccK-P
EPSadr
8.10.2 Start to ISP Data Write/Read In STK6011, the ISP function works following the steps below: 1. Define EEPROM_like slave address. 2. Set SDUP bit to disable Flash software data protection. 3. Set CRCclr bit to reset CRC_register. 4. Define the bank of EEOPRM_like. 5. Set ERASE/BLANK bit to block-erase/chip-erase Flash. 6. Access EEOPRM_like as standard EEPROM. 7. Check CRC_register. 8. Set SDP bit to enable Flash software data protection. 16
STK6011
9. Set CPUclr bit to reset STK6011. The steps between 4 and 6 are recycled until all data are written into Flash. There are four types of I2C bus transfer in EEPROM_like: Byte Write: S-ttttAAA0-k-wwwwwwww-k-dddddddd-k-P Page Write: S-ttttAAA0-k-wwwwwwww-k-dddddddd-k-dddddddd-k- ... -P ... -P Random Read: S-ttttAAA0-k-wwwwwwww-k(-P)-S-ttttAAA1-k-dddddddd-K-P Sequential Read: S-ttttAAA0-k-wwwwwwww-k(-P)-S-ttttAAA1-k-dddddddd-K-dddddddd-KWhere S = start or re-start tttt = EEPROM_like Slave Address AAA = page block address k = ack by slave dddddddd = data The word address automatically increases every time when data byte is transferred. The page size is 256-byte. In STK6011 Flash memory, the program cycle time is 40s. If the ISP slave is not able to complete the program cycle in time, it returns non-ack to the following data byte. In the meantime, the word address does not increase and the CRC does not count the non-acked data byte. wwwwwwww = word address K = ack by host ( 0 or 1) P = stop
8.10.3 Cyclic Redundancy Check (CRC) The ISP Host is able to read the ISP Control Block directly to get the CRC value, instead of reading each byte in Flash. The CRC register counts each data byte acknowledged by the ISP slave during data program period. All bits "1" will be loaded into 16 bits of the CRC register by setting CRCclr bit. MSB is the data byte first shifted into the CRC register. CRCin = CRC[15]^DATAin; CRC[15:0] = {CRC[14]^CRCin, CRC[13:2], CRC[1]^CRCin, CRC[0], CRCin}; Where^ = XOR example: data_byte F6H 28H C3H CRC_register_remainder FFFFH FF36H 34F2H 7031H 17
STK6011
9. MEMORY MAP of XFR
Reg. Name ISPSLV ISPEN ADC ADC WDT PWMDA PWMDA PWMDA PWMDA PWMDA PADOPT PADOPT Addr. Bit 7 0F0Bh(w) 0F0Ch(w) 0F10h (w) ENADC 0F10h (r) 0F18h (w) EWDT 0F20h(r/w) 0F21h(r/w) 0F22h(r/w) 0F23h(r/w) 0F24h(r/w) 0F50h(w) 0F51h(w) PWMf Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ISP Control Block Slave Address Write 93h to enable the ISP mode. SADC3 SADC2 SADC1 SADC0 ADC Converting Result WDTclr WDT2 WDT1 WDT0 Pulse width of PWM DAC 0 Pulse width of PWM DAC 1 Pulse width of PWM DAC 2 Pulse width of PWM DAC 3 Pulse width of PWM DAC 4 AD3E AD2E AD1E AD0E PWMd PWM4E PWM3E PWM2E PWM1E PWM0E Bit 6
18
STK6011
10. ELECTRICAL PARAMETERS 10.1 DC Characteristics Conditions at: Ta=0 ~ 70 oC, VDD=5.0V/3.3V, VSS=0V Name Symbol Conditions Output "L" Voltage Vol Iol=5mA Voh1 VDD=5V, Ioh=-50A Output "H" Voltage on 8051 I/O port pin Voh2 VDD=3.3V, Ioh=-50A Voh3 VDD=5V, Ioh=-4mA Output "H" Voltage on CMOS output Voh4 VDD=3.3V, Ioh=-4mA Vil1 VDD=5V Input "L" Voltage Vil2 VDD=3.3V Vih1 VDD=5V Input "H" Voltage Vih2 VDD=3.3V RST Pull-down Resistor Rrst VDD=5V Pin Capacitance Cio 10.2 AC Characteristics Conditions at: Ta=0 ~ 70 oC, VDD=5.0V/3.3V, VSS=0V Name Symbol Conditions Crystal Frequency fXtal PWM DAC Frequency fDA fXtal=12MHz 10.3 Absolute Maximum Ratings Conditions at: Ta= 0 ~ 70 oC, VSS=0V Name Operating Temperature Storage Temperature Output Voltage Input Voltage Supply Voltage Symbol Topg Tstg Vout Vin VDD5 VDD3 Range 0 ~ +70 -25 ~ +125 -0.3 ~ VDD+0.3 -0.3 ~ VDD+0.3 -0.3 ~ +6.0 -0.3 ~ +4.0 Unit oC oC V V V V Min. 46.875 Typ. 12 Max. 94.86 Unit MHz KHz Min. 4 2.65 4 2.65 -0.3 -0.3 0.4 x VDD 0.6 x VDD 150 Unit V V V V V 0.2 x VDD V 0.3 x VDD V VDD +0.3 V VDD +0.3 V 250 Kohm 15 pF Max. 0.45
10.4 Operating Conditions Allowable Conditions at: Ta= 0 ~ 70 oC, VSS=0V Name Symbol Supply Voltage Operating Freq. VDD Fopg Conditions 5V system 3.3V system Min. 4.5 3.0 Max. 5.5 3.6 15 Unit V V MHz
19
STK6011
11. PACKAGE DIMENSION 11.1 40-Pin PDIP 600 Mil
52.197mm +/-0.127
1.981mm +/-0.254 1.270mm +/-0.254 0.457mm +/-0.127 2.540mm 15.494mm +/-0.254 13.868mm +/-0.102 1.778mm +/-0.127 0.254mm (min.) 0.254mm +/-0.102
3.81mm +/-0.127 3.302mm +/-0.254
5o~70
6o +/-3o 16.256mm +/-0.508
11.2 42-Pin SDIP Unit: mm
Symbo l A A1 B1 D E1 F eB
Dimension in mm
Min 3.937 1.78 0.914 36.78 13.945 15.19 15.24 0
Nom 4.064 1.842 1.270 36.83 13.970 15.240 16.510 7. 5
Max 4.2 1.88 1.118 36.88 13.995 15.29 17.78 1 5
15.494mm +/0.254 13.868mm +/0.102
0.254m m +/-0.102
5o~7
0
20
STK6011
11.3 44-Pin PLCC Unit:
0.045*450
PIN #1 HOLE
0.180 MAX. 0.020 MIN.
0.013~0.021 TYP. 0.690 +/-0.005 0.610 +/-0.02 0.653 +/-0.003 0.500
70TYP. 0.010 0.050 TYP. 0.653 +/-0.003 0.690 +/-0.005 0.026~0.032 TYP. 0.070 0.070
21
STK6011
11.4 44-Pin QFP Unit:
22
STK6011
11.5 48-Pin LQFP Unit:
23
STK6011
12 ORDER INFORMATION
Part No. STK6011-P1 STK6011-P2 STK6011-P3 STK6011-P4 STK6011-P5
Pin Count 40 42 44 44 48
Package DIP SDIP PLCC PQFP LQFP
Marking Syntek Logo STK6011-P1 Manu. No Syntek Logo STK6011-P2 Manu. No Syntek Logo STK6011-P3 Manu. No Syntek Logo STK6011-P4 Manu. No Syntek Logo STK6011-P5 Manu. No
13 CONTACT INFORMATION If you need more detailed information or samples, PLS. contact the next window and then we will make a response to your request as best as we can. / Syntek Semiconductor Co., Ltd.
/ Marketing & Sales Dept. / Marketing Manager / Kevin Liu / Tel : 886 - 3-577-3181 Ext:528
: 886 - 3-577-3181 : 528 : 886 - 3-577-8010
/ Fax : 886 - 3-577-8010
E-mail: cjliu@syntekt.com.tw Mobile: 0936-060871
24

▲Up To Search▲

Price & Availability of STK6011

	To Download STK6011 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .